The electronics industry continues to rely upon advances in semiconductor technology, including integrated circuits (ICs), to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. In addition, many of the individual devices within the wafer are being manufactured with smaller physical dimensions. As the number of electronic devices per given area of the silicon wafer increases, and as the size of the individual devices decreases, testing processes become more important and more difficult.
Many integrated circuit die include circuits that are suspect defects, and these defects can recover or fail under particular operating conditions and at higher temperatures. For instance, circuit sites exhibiting temperature sensitive defects, such as resistive connection, can recover when heated. Traditionally, isolation of IC defects has been attempted by operating the die in a manner that causes a failure to occur and by attempting to attribute the failure to a malfunctioning device in the IC. Such electrical testing, however, does not always work because many failures and malfunctions can result from a variety of different types of defects and defects at non-suspect circuitry locations.
One such defect that can cause difficulty in determining the cause of a failure in an IC is a resistive electrical connection. Resistive interconnections have been a major IC manufacturing problem in terms of yield, performance, and reliability, and this problem is expected to increase in importance as the number of interconnection levels and operating frequencies increase. While the ability to localize these defective interconnections can be extremely useful for diagnosing IC failures and implementing corrective action, unfortunately, resistive interconnections on failing ICs can be difficult and time consuming to localize because they often require high frequency operation to produce a functional failure and a great deal of repetitive probing to identify.
Defect localization is complicated by the employment of multiple levels of metal interconnections that obscure lower conductor levels. For flip-chip packaging in which the die is packaged top-side down, front side examination techniques of the die are often extremely difficult and time-consuming. These difficulties have led to the development and use of more advanced IC analysis techniques involving both back side and front side approaches, including those discussed in “TIVA and SEI Developments for Enhanced Front and Backside Interconnection Failure Analysis”, ESREF, pp. 991-996 (1999), by E. I. Cole Jr., P. Tangyunyong, E. S. Benson, and D. L. Barton. Unfortunately, previously known methods, such as infrared optical microscopy, light emission microscopy, and transistor logic state mapping are not effective in localizing resistive interconnections.